Gate array system in which functional blocks are connected by fixed wiring

ABSTRACT

An gate array system characterized in including, on a semiconductor chip, an internal cell region where internal cells are arranged in lattice and a cell region for input/output circuit including an array of input/output circuit cells disposed on the circumference of the internal cell region, and characterized in that a positional relationship between an internal cell at a specific position of the internal cell region and a specific input/output cell constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of a semiconductor chip.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a gate array system and a layout method thereof and, more particularly, to a gate array system in which functional blocks disposed at specific positions are connected by fixed wiring using a fixed layout pattern prepared in advance and a layout method thereof.

2. Description of the Related Art

A gate array system implemented on a semiconductor chip includes a lattice array of internal cells, an array of input/output circuit cells (hereinafter referred to as I/O cell) disposed surrounding the lattice array of the internal cells for receiving a signal from and transferring a signal to these internal cells, and a bonding pad array disposed on the circumference of the semiconductor chip surrounding the array of the I/O cells for connecting the gate array system and an external circuit. These configurations are made up in advance by the manufacturing processes on a uniform mass-production basis. In addition, for the manufacture of various gate array systems, a plurality of types of semiconductor chips of difference sizes are prepared by the manufacturing processes on a mass-production basis.

FIG. 7 is a partial layout diagram showing an example of structure of the above-described conventional gate array. On the gate array system illustrated in FIG. 7, connecting functional blocks formed on internal cells 702 is possible by mechanical automatic wiring, fixed wiring using a specific layout pattern, or other arbitrary means. However, connection of a functional block formed at a corner of a semiconductor chip 701 or on an I/O cell 703 with a functional block formed on the internal cell 702 in the vicinity of the former functional block by automatic wiring is difficult because of the crowdedness of a wiring area at this region or because of difficulty in satisfying desired electric characteristics. For connecting functional blocks formed at this region, it is a conventional practice to manually modify the connection which is once made by automatic wiring, or conduct manual wiring from the beginning, or conduct fixed wiring using a fixed layout pattern prepared in advance for the wiring of the region in question.

In conducting fixed wiring using a fixed layout pattern, the above-described conventional gate array system implements a desired function without automatic wiring by making a functional block formed at an internal cell region or a functional block formed at an I/O cell region have a layout pattern of fixed wiring for the wire connection and disposing the functional block at an appropriate position. However, because the distance between an internal cell and an I/O cell varies with the size of a semiconductor chip, as will be described later, it is necessary to prepare in advance as many fixed layout patterns of the parts in question that implement the same function as the number of sizes of a semiconductor chip.

Internal cells and I/O cells are optimized according to a manufacturing process and a circuit in which they are used and are designed to be of minimum size for the purpose of increasing the integration density. As a result, a distance between an internal cell and an I/O cell is not always constant on a semiconductor chip of each size, considering the sizes of a semiconductor chip, internal cells and I/O cells. The reasons are as follows.

Assume, for example, that a semiconductor chip of a gate array system with the size of 8.3 mm×8.3 mm is A chip and a semiconductor chip with the size of 14.9 mm×14.9 mm is B chip. On both of the A and B chips, the size of an internal cell is assumed to be 7.4 μm×28.6 μm, the size of an I/O cell to be 100 μm×368.7 μm and the distance from the edge of the semiconductor chip to the edge of the I/O cell to be 160 μm. As a result, the internal cells are arranged in a lattice array symmetrically to the center of the semiconductor chip. Here, if the distance in the X direction of the semiconductor chip between the internal cell and the I/O cell is represented as Dx and the distance in the Y direction between the internal cell and the I/O cell as Dy, the A chip will have Dx of 51.5 μm and Dy of 59.1 μm, while the B chip will have Dx of 51.3 μm and Dy of 50.3 μm, which are different from each other.

If a value obtained by subtracting the size of the I/O cell and the distance between the edge of the semiconductor chip and the edge of the I/O cell from the size of the semiconductor chip is represented as K, Dx will have a value obtained by subtracting, from K, a value obtained by multiplying the size in the X direction of the internal cell by the number of lattice arrays in the X direction of the internal cells in question, while Dx will similarly have a value obtained by subtracting, from K, a value obtained by multiplying the size in the Y direction of the internal cells by the number of lattice arrays in the Y direction of the internal cells in question. Concrete calculation of the distance Dx in the X direction between the internal cell and the I/O cell on the A chip results in K=8300/4-368.7-160=1546.8 μm. Assuming the optimum number of arrays in the X direction of the internal cells to be 202, then Dx=K-7.4×202=51.5 μm.

General expression of these relationships is given in the X direction of the semiconductor chip. As illustrated in FIG. 7, formed in advance on the semiconductor chip 701 by the manufacturing processes on a mass-production basis are a lattice array of internal cells 702, an array of I/O cells 703 disposed surrounding the lattice array for receiving a signal from and transferring a signal to the internal cells 702, and an array of bonding pads 704 disposed on the circumference of the semiconductor chip surrounding the array of the I/O cells 703 for connecting the circuits formed on the semiconductor chip 701 with an external circuit. If the size of the semiconductor chip 701 in the X direction is represented as X1, the size of the internal cell 702 in the X direction as X2, the number of arrays of internal cells in the X direction as nx and the distance in the X direction from the edge of the semiconductor chip 701 to the edge of the I/O cell 703 as X3, the relationship X1=2×Dx+nx×X2+2×X3 holds. Here, the conditions for maintaining the distance Dx to be constant with the value of X1 largely depend on the size of the internal cell 702. Taking into account of the fact that the size of the internal cell 702 is minimized for the purpose of increasing the integration density, obtaining a constant distance Dx is very difficult. While general description has been made with respect to the X direction in the foregoing, this is also the case with the Y direction.

FIG. 8 is a flow chart showing a layout method for implementing a desired function on a conventional gate array system by wiring a functional block formed at a corner of the semiconductor chip or on an I/O cell and a functional block formed on an internal cell in the vicinity of the former block.

First, select a functional block optimum for implementing a desired function (Step 801). The functional block used in this example is designed to include, in its internal region, a fixed layout pattern for the wire connection. Next, determine automatic locating and wiring information, using wiring information included in the functional block (Step 802). Then, conduct automatic locating and wiring, using the determined automatic locating and wiring information (Step 803).

The above-described conventional gate array system and layout method thereof, however, have the following drawbacks when implementing a desired function by wiring a functional block formed at a corner of a semiconductor chip or on an I/O cell and a functional block formed on an internal cell in the vicinity of the former block.

Firstly, the conventional gate array system requires as many fixed layout patterns of functional blocks in question which implement the same function to be prepared in advance as the number of sizes of a semiconductor chip. The reason is that since a distance in layout between an internal cell and an I/O cell varies with each size of a semiconductor chip, a gate array system should cope with a difference in distance in layout when conducting fixed wiring using a fixed layout pattern included in a functional block. This results in an increase in the number of steps for designing the fixed layout pattern of the functional block, that is, results in a reduction in efficiency. Moreover, there would exist numbers of similar functional blocks that only differ in wiring of a fixed layout pattern, which causes a designing error to be liable to occur.

Secondly, since wires are crowded at a corner of a semiconductor chip or in the vicinity of an I/O cell, there are cases where automatic wiring is impossible and where required electric characteristics are not satisfied. Repetition of re-wiring processing or manual wiring of some part or the whole part is therefore necessary and numerous designing steps and enormous designing time cause a reduction in efficiency.

Thirdly, the layout method of the conventional gate array system employs neither information regarding a positional relationship between an internal cell and an I/O cell nor information regarding a locating position of a functional block at the time of layout. For locating functional blocks at optimum positions, therefore, their locating positions should be designated one by one, which requires a larger number of designing steps and makes a designing error more likely to occur.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a gate array system which enables connection of a functional block formed on an I/O cell region of a semiconductor chip and a functional block formed on an internal cell in the vicinity of the former block by fixed wiring using one type of fixed layout pattern irrespective of the size of the semiconductor chip, thereby preventing a designing error, and a layout method thereof.

Another object of the present invention is to provide a gate array system which enables reduction in the number of designing steps and designing time to improve working efficiency by connecting functional blocks at a corner of a semiconductor chip or in the vicinity of an I/O cell by fixed wiring using a uniform fixed layout pattern irrespective of the size of the semiconductor chip and connecting functional blocks at other areas by conventional automatic wiring, and a layout method thereof.

Still another object of the present invention is to provide a gate array system which is structured to have a constant distance between an internal cell at a specific area of a lattice array of internal cells and a specific I/O cell irrespective of the size of a semiconductor chip to enable use of information regarding a positional relationship between the internal cell and the I/O cell and a locating position of a function block in question, and a layout method thereof.

According to one aspect of the invention, a gate array system in which at least a part of functional blocks are connected by fixed wiring using a fixed layout pattern prepared in advance, comprises

on a semiconductor chip, an internal cell region where internal cells are arranged in lattice and a cell region for input/output circuit including an array of input/output circuit cells disposed on the circumference of the internal cell region, wherein

a positional relationship between the internal cell at a specific position of the internal cell region and a specific one of the input/output cells constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of the semiconductor chip.

The internal cell region is divided into a plurality of regions, and a positional relationship between the internal cells constituting at least one region of the plurality of regions and a specific one of the input/output cells constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of the semiconductor chip.

In the preferred construction, the internal cell region is square as a whole and is made up of a first region formed at a corner of the square and a second region having a shape obtained by cutting out the first region from the square, and a positional relationship between the internal cells constituting the first region and a specific one of the input/output cells constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of the semiconductor chip.

In the preferred construction, the internal cell region is square as a whole and is made up of four first regions formed at the four corners of the square and a second region having a shape obtained by cutting out the first regions from the square, and a positional relationship between the internal cells constituting at least one of the first regions and a specific one of the input/output cells constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of the semiconductor chip.

In another preferred construction, the internal cell region is square and the input/output cells arranged at the input/output cell region form four input/output cell arrays each parallel to each side of the square internal cells, and the distance in layout between an array of the internal cells forming at least one side of the square internal cell region and the input/output cell array parallel to the side of the internal cell region is constant irrespective of the size of the semiconductor chip.

In another preferred construction, the internal cell region is square and the input/output cells arranged at the input/output cell region form four input/output cell arrays each parallel to each side of the square internal cells, and the distance in layout between an array of the internal cells forming arbitrary two adjacent sides of the square internal cell region and two adjacent the input/output arrays respectively parallel to the two sides of the internal cell region is constant irrespective of the size of the semiconductor chip.

According to another aspect of the invention, a layout method of locating and wiring a functional block using a gate array which includes, on a semiconductor chip, an internal cell region having internal cells arranged in lattice and a cell region for input/output circuit including an array of input/output circuit cells disposed on the circumference of the internal cell region, comprising the steps of:

manufacturing the gate array such that a positional relationship between the internal cell at a specific position of the internal cell region and a specific one of the input/output cells constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of the semiconductor chip,

selecting a functional block optimum for realizing a desired function,

determining whether when the functional block selected at the selection step is formed at the internal cell and at the input/output circuit cell or at the specific position of the cell region for input/output circuit whose positional relationship is all specified, connection of the functional blocks is possible by fixed wiring using a fixed layout pattern included in the functional block,

when the determination is made at the determination step that the functional block selected at the selection step can be connected by fixed wiring using a fixed layout pattern, locating the functional block at an optimum position on the semiconductor chip, and

connecting the functional block located on the semiconductor chip at the locating step and other functional block by automatic locating and wiring processing, as well as locating, at appropriate positions of the internal cell region, all the functional blocks whose connection by fixed wiring using a fixed layout pattern is determined to be impossible at the determination step and connecting the blocks by automatic locating and wiring processing.

In this case, the locating step comprises the steps of obtaining information regarding a positional relationship between the internal cell and the input/output circuit cell and a locating position of the functional block on the semiconductor chip, and determining an optimum locating position of the functional block on the semiconductor chip to locate the functional block based on the obtained information.

Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only.

In the drawings:

FIG. 1 is a layout diagram showing structure of a gate array system according to a first embodiment of the present invention.

FIG. 2 is an expanded layout diagram showing an expansion of a region A surrounded by a broken line illustrated in FIG. 1.

FIG. 3 is an expanded layout diagram showing a further expansion of the region A surrounded by the broken line illustrated in FIG. 1.

FIG. 4 is a layout diagram showing structure of a gate array system according to a second embodiment of the present invention.

FIG. 5 is an expanded layout diagram showing an expansion of a region B surrounded by a broken line illustrated in FIG. 4.

FIG. 6 is a flow chart showing a flow of the locating and wiring processing by the gate array system of the present invention.

FIG. 7 is a partial layout diagram showing structure of a conventional gate array system.

FIG. 8 is a flow chart showing a flow of the locating and wiring processing by a conventional gate array system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiment of the present invention will be discussed hereinafter in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to those skilled in the art that the present invention may be practiced without these specific details.

FIG. 1 is a layout diagram showing structure of a gate array system according to a first embodiment of the present invention.

With reference to FIG. 1, the gate array system of the present embodiment includes, on a semiconductor chip 101, a lattice array of internal cells 102, an array of I/O cells 103 disposed surrounding the lattice array of the internal cells 102 for receiving signals from and transferring signals to the internal cells 102, and an array of bonding pads 104 disposed on the circumference of the semiconductor chip 101 surrounding the array of the I/O cells 103 for connecting the gate array system and external circuits. These configurations are made up in advance by the manufacturing processes on a uniform mass-production basis. In addition, for the manufacture of various gate array systems, a plurality of kinds of semiconductor chips 101 of different sizes are prepared by the manufacturing processes on a mass-production basis as is done for conventional gate array systems.

The lattice array of the internal cells 102 is comprised of internal cell arrays 102A formed at the four corners of the lattice array and an internal cell array 102B formed at the remaining area. The internal cell array 102A has specific form and size irrespective of the size of the semiconductor chip 101 and is placed at a fixed distance in layout from each of the adjacent arrays of the I/O cells 103. The internal cell array 102B is located at the center of the semiconductor chip 101, with the four corners of its square cut to meet the form of the internal cell arrays 102A. Between the internal cell array 102A and the internal cell array 102B, a gap is generated according to the size of the semiconductor chip 101 and its space is not uniform.

On the semiconductor chip 101 shown in FIG. 1, a functional block 105 is fixedly formed at the lower left corner as illustrated in the figure. The functional block 105 is connected to a functional block 109 formed on the internal cell array 102A as illustrated in FIG. 2 which is the expanded layout diagram of the area A surrounded by the broken line in FIG. 1.

With reference to FIG. 2, the functional block 109 is made up of three of the internal cells 102 which constitute the internal cell array 102A. The functional block 109 also includes a fixed layout pattern which forms a fixed wire 106. Locating the functional block 109 at a predetermined position therefore enables connection with the functional block 105 formed at a corner of the semiconductor chip 101 through the wire 106 formed according to the fixed layout pattern. Here, since distances 107 and 108 between the internal cells 102 constituting the internal cell array 102A and the I/O cells 103 are constant irrespective of the size of the semiconductor chip 101 as described above, wiring using a common fixed layout pattern is possible for connecting the functional block 105 formed at a corner and the functional block 109 formed on the internal cell array 102A on the semiconductor chip 101 of different size. For connecting the same type of functional blocks, it is therefore only necessary to prepare one type of fixed layout pattern.

While this embodiment has been described with respect to a case where the functional block 109 made up of the internal cells 102 includes a fixed layout pattern for the connection with the functional block 105 formed at the corner of the semiconductor chip 101, it is clear that the same effect can be obtained when by contraries, the functional block 105 formed at a corner of the semiconductor chip 101 includes a fixed layout pattern for the connection with the functional block 109 made up of the internal cells 102. In addition, although in the present embodiment, description has been made with respect to wiring according to fixed layout for connecting the functional block 105 formed at a corner of the semiconductor chip 101 with the functional block 109 made up of the internal cells 102, the same description will be applicable to wiring according to fixed layout for connecting a functional block formed on the I/O cell 103 with the functional block 109 made up of the internal cells 102.

In addition, the gap between the internal cell array 102A and the internal cell array 102B varies with the size of the semiconductor chip 101 as described above. Even when a distance between the internal cells 102 varies, however, it can be coped with, similarly to the conventional art, by appropriately setting a wiring lattice for automatic wiring because connection of functional blocks at an internal area will be made by automatic wiring.

In addition to the provision of the internal cell arrays 102A at a constant distance in layout from the I/O cell 103 at four corners of the lattice array of the internal cells 102 as is done in the present embodiment, an internal cell array may be formed at an arbitrary position in the lattice array of the internal cells 102 so as to have a constant distance in layout from an arbitrary I/O cell 103. Also in this case, a functional block formed on the I/O cell 103 in question and a functional block formed on the internal cell array in question can be wired using a fixed layout pattern. Type of internal cells constituting such an internal cell array may be different from or the same as that of internal cells at other regions and the number of arrays is not limited. As an extreme example, a lattice array of the internal cells 102 may be divided into four to form the internal cell arrays 102A without provision of the internal cell array 102B.

Furthermore, in an actual gate array system, a distance in layout between an internal cell and an I/O cell 103 is not strictly equal in every semiconductor chip in some cases due to an error in manufacture, like 51 μm on one semiconductor chip and 49 μm on the other semiconductor chip. However, providing a wiring data connection pattern with an overlapping part on the order of several μm can cancel such an error to enable appropriate wiring. Detailed description thereof will be made with reference to the expanded layout diagram of FIG. 3.

With reference to FIG. 3, the wire 106 connects the functional block 105 and the functional block 109 made up of the internal cells 102. At this time, assuming an overlap 111 of a connection pattern 110 in the functional block 105 with the wire 106 to be 2 μm, for example, appropriate wiring is possible even when the distance 107 in layout between the internal cell 102 and the I/O cell 103 has an error on the order of 2 μm.

FIG. 4 is a layout diagram showing structure of a gate array system according to a second embodiment of the present invention.

With reference to FIG. 4, the gate array system of the present embodiment, as well as the above-described first embodiment, includes on a semiconductor chip 201, a lattice array 202 of internal cells 102, an array of I/O cells 103 disposed surrounding the lattice array of the internal cells 102 for receiving and transferring a signal from/to the internal cells 102, and an array of bonding pads 104 disposed on the circumference of the semiconductor chip 201 surrounding the array of the I/O cells 103 for connecting the gate array system and external circuits. These configurations are made up in advance by the manufacturing processes on a uniform mass-production basis. In addition, as well as the first embodiment and conventional art, a plurality of kinds of semiconductor chips 201 of different sizes are prepared by the manufacturing processes on a mass-production basis for manufacturing various gate array systems.

The lattice array 202 of the internal cells 102 is disposed at a fixed distance from one pair of adjacent arrays of I/O cells 103 irrespective of the size of a semiconductor chip. More specifically, the distance in layout between the column of internal cells 102 located on the left end in FIG. 4 and the left side array of the I/O cells 103 and the distance in layout between the row of internal cells 102 located on the lower end and the lower side array of the I/O cells 103 are set to be constant irrespective of the size of a semiconductor chip. It is seen from FIG. 5, which is an expanded layout diagram of the area B surrounded by the broken line illustrated in FIG. 4, that a distance 207 between the internal cell 102 and the left side I/O cell 103 and a distance 208 between the internal cell 102 and the lower I/O cell 103 are constant. The distance between the column of the internal cells 102 located on the right end in FIG. 4 and the right side array of the I/O cells 103 and the distance between the row of the internal cells 102 located on the upper end and the upper array of the I/O cells 103 are not constant.

With reference to FIG. 5, a functional block 205 is formed on the left end I/O cell 103 of the lower side array of the I/O cells 103 and a functional block 209 is made up of nine internal cells 102 on the lower left corner of the lattice array 202 of the internal cells 102, and the two blocks are connected by a wire 206 formed according to a fixed layout pattern. The fixed layout pattern is included in the functional block 209 made up of the internal cells 102. Therefore, by locating the functional block 209 at a predetermined position, connection with the functional block 205 formed of the I/O cell 103 is possible via the wire 206 formed according to the fixed layout pattern. Here, since a specific part of the lattice array 202 of the internal cells 102 is laid out to have a fixed distance from the I/O cell 103, connection between the functional block 205 formed of the I/O cell 103 and the functional block 209 made up of the internal cells 102 on the semiconductor chips 201 of different sizes is possible by wiring using a common fixed layout pattern as a result of use of the specific part to conduct fixed wiring using a fixed layout pattern. Connection of functional blocks of the same type therefore only requires one type of fixed layout pattern to be prepared.

Although the present embodiment has been described with respect to a case where the functional block 209 made up of the internal cells 102 includes a fixed layout pattern for the connection with the functional block 205 formed of the I/O cell 103, it is clear that the same effect can be obtained even when by contraries, the functional block 205 formed of the I/O cell 103 includes a fixed layout pattern for the connection with the functional block 209 made up of the internal cells 102. In addition, although in the present embodiment, description has been made with respect to the wiring according to fixed layout for connecting the functional block 205 made of the I/O cell 103 with the functional block 209 made up of the internal cells 102, the same description is also applicable to the wiring according to fixed layout for connecting a functional block formed at a corner of the semiconductor chip 201 with the functional block 209 made up of the internal cells 102.

As described in the foregoing, the distance between the column of the internal cells 102 located on the right end and the right side array of the I/O cells 103 and the distance between the row of the internal cells 102 located on the upper end and the upper side array of the I/O cells 103 in FIG. 4 vary with the size of the semiconductor chip 201. The region in question, however, can be coped with by automatic wiring as in conventional art by appropriately setting a wiring lattice for automatic wiring without execution of fixed wiring using the fixed layout pattern of the present embodiment.

An area in which the distance in layout between the internal cell 102 and the I/O cell 103 is set to be constant is not limited to two adjacent sides shown in the present embodiment. As long as the distance between an arbitrary simple substance or a plurality of internal cells 102 and an arbitrary simple substance or a plurality of I/O cells 103 is fixed in layout structure, the present embodiment is applicable to a functional block made up of the internal cells 102 in question and a functional block formed of the I/O cell 103 in question to produce the same effect.

Moreover, as in the above-described first embodiment, providing a wiring data connection pattern with an overlapping part on the order of several μm enables cancellation of a manufacturing error in an actual gate array system to realize appropriate wiring.

Next, with reference to the flow chart of FIG. 6, description will be made of a flow of the locating and wiring processing by the gate array system according to the above-described first or second embodiment of the present invention.

First, select a functional block optimum for realizing a desired function (Step 601). Then, determine whether the selected functional block is suitable for the above fixed wiring using a fixed layout pattern according to the above embodiment (Step 602). Taking the first embodiment as an example, determination is made with reference to wiring information of the functional block selected at Step 601 whether when the functional block selected at Step 601 is placed at a corner of the semiconductor chip 101 and at the internal cell array 102A in the vicinity of the corner in question, a fixed layout pattern which can be realized by fixed wiring is set at the functional block in question.

When the determination is made at Step 602 that the selected block is suitable, then obtain information regarding a positional relationship between the internal cell 102 and the I/O cell 103 and a locating position of the functional block in question (Step 603) to determine a locating position of each functional block (Step 604). The information obtained at Step 603 is acquired through reading from an appropriate data base prepared in advance. The present invention can use these information because a positional relationship between an internal cell 102 and an I/O cell 103 at a specific region is fixed.

After the decision of a locating position of the functional block, locate other functional block at an internal cell region, as well as determining automatic locating and wiring information for automatic wiring with other functional block in question by using wiring information included in the functional block in question (Step 605) to conduct wiring with other functional block in question by automatic locating and wiring processing based on the automatic locating and wiring information (Step 606). The automatic locating and wiring processing is conducted in the conventional manner.

When the determination is made at Step 602 that the selected functional block is not suitable for the connection by fixed wiring using a fixed layout pattern according to the present invention, locate all the functional blocks to be connected to the functional block in question by using wiring information included in the functional block in question, as well as determining automatic locating and wiring information for automatic wiring between the functional blocks in question (Step 605) to conduct automatic locating and wiring processing based on the automatic locating and wiring information (Step 606).

As described in the foregoing, since according to the gate array system and its layout method of the present invention, the gate array system is structured such that the distance between an internal cell at a specific region of a lattice array of internal cells and a specific I/O cell is constant irrespective of the size of a semiconductor chip, in the implementation of a desired function by the connection of a functional block formed at a corner of an I/O cell region or on an I/O cell on the semiconductor chip and a functional block made up of internal cells in the vicinity of the former block by fixed wiring using a fixed layout pattern included in the functional block in question, a common functional block including one type of fixed layout pattern can be used even on semiconductor chips of different sizes. As a result, it is unnecessary to prepare as many fixed layout patterns of a functional block as the number of sizes of a semiconductor chip, which prevents a designing error.

The present invention has another effect of reducing the number of designing steps and designing time to improve working efficiency at a corner of a semiconductor chip or in the vicinity of an I/O cell where wires are crowded because functional blocks at a corner of a semiconductor chip or in the vicinity of an I/O cell are connected by fixed wiring using a given fixed layout pattern irrespective of the size of the semiconductor chip and functional blocks at other regions are connected by conventional automatic wiring.

Moreover, being structured to have a constant distance between an internal cell at a specific region of a lattice array of internal cells and a specific I/O cell irrespective of the size of a semiconductor chip, the present invention enables use of information regarding a positional relationship between an internal cell and an I/O cell and regarding locating position of a functional block in question. This eliminates the need of designating a locating position one by one for locating a functional block at an optimum position, thereby reducing the number of designing steps to prevent a designing error.

Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set out in the appended claims. 

What is claimed is:
 1. A gate array system in which at least a part of functional blocks are connected by fixed wiring using a fixed layout pattern prepared in advance, comprising:on a semiconductor chip, an internal cell region where internal cells are arranged in lattice and a cell region for input/output circuit including an array of input/output circuit cells disposed on the circumference of the internal cell region; wherein a positional relationship between said internal cell at a specific position of said internal cell region and one of a specific one of said input/output cells constituting said cell region for input/output circuit and a functional block formed at a specific position of said cell region for input/output circuit is constant irrespective of the size of said semiconductor chip.
 2. The gate array system as set forth in claim 1, whereinsaid internal cell region is divided into a plurality of regions, and a positional relationship between said internal cells constituting at least one region of said plurality of regions and said specific one of said input/output cells constituting said cell region for input/output circuit and said functional block formed at said specific position of said cell region for input/output circuit is constant irrespective of the size of said semiconductor chip.
 3. The gate array system as set forth in claim 1, whereinsaid internal cell region is square as a whole and is made up of a first region formed at a corner of the square and a second region having a shape obtained by cutting out the first region from the square, and a positional relationship between said internal cells constituting said first region and said one of said specific one of said input/output cells constituting said cell region for input/output circuit and said functional block formed at said specific position of said cell region for input/output circuit is constant irrespective of the size of said semiconductor chip.
 4. A gate array system in which at least a part of functional blocks are connected by fixed wiring using a fixed layout pattern prepared in advance, comprising:on a semiconductor chip, an internal cell region where internal cells are arranged in lattice and a cell region for input/output circuit including an array of input/output circuit cells disposed on the circumference of the internal cell region; wherein said internal cell region is square as a whole and is made up of four first regions formed at the four corners of the square and a second region having a shape obtained by cutting out the first regions from the square, and a positional relationship between said internal cells constituting at least one of said first regions and a specific one of said input/output cells constituting said cell region for input/output circuit and a functional block formed at a specific position of said cell region for input/output circuit is constant irrespective of the size of said semiconductor chip.
 5. The gate array system as set forth in claim 1, whereinsaid internal cell region is square and said input/output cells arranged at said input/output cell region form four input/output cell arrays each parallel to each side of said square internal cells, and the distance in layout between an array of the internal cells forming at least one side of said square internal cell region and said input/output cell array parallel to the side of the internal cell region is constant irrespective of the size of said semiconductor chip.
 6. The gate array system as set forth in claim 1, whereinsaid internal cell region is square and said input/output cells arranged at said input/output cell region form four input/output cell arrays each parallel to each side of said square internal cells, and the distance in layout between an array of the internal cells forming arbitrary two adjacent sides of said square internal cell region and two adjacent said input/output arrays respectively parallel to the two sides of the internal cell region is constant irrespective of the size of said semiconductor chip.
 7. A gate array structure disposed on a semiconductor chip, said structure comprising:an internal cell region comprising a plurality of internal cells arranged in a lattice structure; an input/output cell region comprising a plurality of input/output cells disposed on the circumference of said internal cell region; a fixed layout pattern comprising a plurality of wires connecting at least one of said internal cells with at least one of said input/output cells, said plurality of wires having a substantially fixed length irrespective of the size of said semiconductor chip.
 8. A gate array structure according to claim 7, said input/output cell region further comprising a functional block and said at least one input/output cell connected by said plurality of wires is said functional block. 